As the number of devices such as transistors, diodes, capacitors, resistors, etc. on an integrated circuit increases, the complexity of interconnecting the devices often exceeds the capability of providing a corresponding interconnecting pattern on a single conductive layer. Providing several interconnection levels is highly desirable in very large scale integrated circuit technology, as it allows both higher packing density of the active components and greater freedom in their placement on the chip. Thus the denser integrated circuits have now required the use of two or more conductive layers to provide the required interconnections, with the two or more conductive layers being separated by an electrically insulating layer.
In conventional chip manufacturing, the silicon wafer is first oxidized to form a SiO.sub.2 layer on the surface. Photoresist is then applied to the silicon wafer, dried, and then exposed with the proper geometrical pattern. After exposure, the wafer is soaked in a solution that develops the images in the photosensitive material. Depending on the type of polymer used for the photoresist, either exposed or unexposed areas of film are removed in the developing process. The wafer is then placed in an environment (e.g., a chemical solution), that etches surface areas not protected by the polymer pattern. Finally, the resist is stripped, leaving behind a SiO.sub.2 image which then becomes a mask for subsequent processing. For example, an ion implant would dope the exposed silicon, but not the silicon covered by the oxide. After the SiO.sub.2 is stripped, the silicon surface is left with a dopant pattern that duplicates the design pattern on the photomask. The complete circuit is built up by aligning the next photomask in the sequence to the pattern in the silicon and repeating the entire process, until all the components of the circuit have been constructed. All the individual components must now be connected together with a conductor pattern. When more than one level of conductors is necessary, then the levels must be separated with a dielectric layer. Electrical passages through holes in the dielectric, referred to as "vias", are formed to enable conduction between levels of conductors at the desired locations.
It is apparent that the above described method of integrated circuit chip manufacturing is complicated, time-consuming and expensive.
It is therefore an object of the present invention to provide an effective, but less complicated and less expensive method of integrated circuit chip manufacturing, when more than one level of conductors is needed.
The present invention utilizes a two-step process for converting an ordinary photoresist composition to a useful dielectric in a semiconductor chip. First, the photoresist material (after undesired photoresist is removed is exposed to a xenon flash light, as taught in U.S. Pat. No. 4,443,533, the disclosure of which is hereby incorporated by reference for exposure intensities, flash duration and other required parameters. This stabilizes the photoresistist and enables it to withstand temperatures up to 600.degree. C. or more. In this condition, however, the photoresist contains volatile components (e.g., solvents). In the past, therefore, as shown in U.S. Pat. No. 4,443,533, the photoresist was eventually removed completely from the chip. However, in the present invention, instead of removing the photoresist after the steps of masking and developing, it is converted to a permanent dielectric by baking the chip at a high temperature (e.g., 300.degree.-400.degree. C. or more), to remove the volatile components photoresist. After baking, the photoresist is stable, has good dielectric properties, resists flowing at temperatures up to 600.degree. C. or more, and functions in much the same manner as the prior art dielectric layer formed of oxide, nitride or the like. The converted photoresist can be used as a permanent dielectric. Therefore, fewer steps are necessary to achieve the same results during the manufacturing.
Thus the prior art steps of depositing an insulation layer before applying photoresist, ion or plasma etching that insulation layer to establish vias and then removing the remaining photoresist are eliminated. The vias are formed directly as part of the process of masking the photoresist and removing unwanted material.
This saves substantial expenses for capital equipment (such as the etching equipment), time and material, thereby reducing the cost of manufacturing.